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Multiplexer

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Image:Multiplexer2.png
Schematic of a 2-to-1 Multiplexer. It can be equated to a controlled switch.
Image:Demultiplexer.png
Schematic of a 1-to-2 Demultiplexer. Like a multiplexer, it can be equated to a controlled switch.

In electronics, a multiplexer or mux (occasionally the term muldex is also found, for a combination multiplexer-demultiplexer) is a device that performs multiplexing; it selects one of many analog or digital input signals and outputs that into a single line.

An electronic multiplexer makes it possible for several signals to share one expensive device or other resource, for example one A/D converter or one communication line, instead of having one device per input signal.

In electronics, a demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. A multiplexer is often used with a complementary demultiplexer on the receiving end.

An electronic multiplexer can be considered as a multiple-input, single-output switch, and a demultiplexer as a single-input, multiple-output switch. The schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins and the short parallel side containing the output pin. The schematic on the right shows a 2-to-1 multiplexer on the left and an equivalent switch on the right. The Failed to parse (Missing texvc executable; please see math/README to configure.): sel

wire connects the desired input to the output.

In telecommunications, a multiplexer is a device that combines several input information signals into one output signal, which carries several communication channels, by means of some multiplex technique. A demultiplexer is in this context a device taking a single input signal that carries many channels and separates those over multiple output signals.

Multiplex
techniques
Circuit mode
(constant bandwidth)
TDM · FDM · WDM
Polarization multiplexing
Spatial multiplexing (MIMO)
Statistical multiplexing
(variable bandwidth)
Packet mode · Dynamic TDM
FHSS · DSSS · OFDMA
Related topics
Channel access methods
Media Access Control (MAC)

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In telecommunications and signal processing, an analog time division multiplexer (TDM MUX) may take several samples of separate analogue signals and combine them into one pulse amplitude modulated (PAM) wide-band analogue signal. Alternatively, a digital TDM multiplexer may combine a limited number of constant bit rate digital data streams into one data stream of a higher data rate, by forming data frames consisting of one timeslot per channel.

In telecommunications, computer networks and digital video, a statistical multiplexer may combine several variable bit rate data streams into one constant bandwidth signal, for example by means of packet mode communication. An inverse multiplexer may utilize several communication channels for transferring one signal.

Contents

Cost savings

Image:Telephony multiplexer system.gif
The basic function of a multiplexer: combining multiple inputs into a single data stream. On the receiving side, a demultiplexer splits the single data stream into the original multiple signals.

One use for multiplexers is cost savings by connecting a multiplexer and a demultiplexer (or demux) together over a single channel (by connecting the multiplexer's single output to the demultiplexer's single input). The image to the right demonstrates this. In this case, the cost of implementing separate channels for each data source is more expensive than the cost and inconvenience of providing the multiplexing/demultiplexing functions. In a physical analogy, consider the merging behaviour of commuters crossing a narrow bridge; vehicles will take turns using the few available lanes. Upon reaching the end of the bridge they will separate into separate routes to their destinations.

At the receiving end of the data link a complementary demultiplexer is normally required to break single data stream back down into the original streams. In some cases, the far end system may have more functionality than a simple demultiplexer and so, whilst the demultiplexing still exists logically, it may never actually happen physically. This would be typical where a multiplexer serves a number of IP network users and then feeds directly into a router which immediately reads the content of the entire link into its routing processor and then does the demultiplexing in memory from where it will be converted directly into IP packets.

It is usual to combine a multiplexer and a demultiplexer together into one piece of equipment and simply refer to the whole thing as a "multiplexer". Both pieces of equipment are needed at both ends of a transmission link because most communications systems transmit in both directions.

A real world example is the creation of telemetry for transmission from the computer/instrumentation system of a satellite, space craft or other remote vehicle to a ground system.

In analog circuit design, a multiplexer is a special type of analog switch that connects one signal selected from several inputs to a single output.

Digital multiplexers

In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect Failed to parse (Missing texvc executable; please see math/README to configure.): I_0

to the output while a logic value of 1 would connect Failed to parse (Missing texvc executable; please see math/README to configure.): I_1
to the output.

In larger multiplexers, the number of selector pins is equal to Failed to parse (Missing texvc executable; please see math/README to configure.): \left \lceil \log_2(n) \right \rceil

where Failed to parse (Missing texvc executable; please see math/README to configure.): n
is the number of inputs.

For example, 9 to 16 inputs would require no less than 4 selector pins and 17 to 32 inputs would require no less than 5 selector pins. The binary value expressed on these selector pins determines the selected input pin.

A 2-to-1 multiplexer has a boolean equation where Failed to parse (Missing texvc executable; please see math/README to configure.): A

and Failed to parse (Missing texvc executable; please see math/README to configure.): B
are the two inputs, Failed to parse (Missing texvc executable; please see math/README to configure.): S
is the selector input, and Failed to parse (Missing texvc executable; please see math/README to configure.): Z
is the output:
Failed to parse (Missing texvc executable; please see math/README to configure.): Z = ( A \cdot \overline{S}) + (B \cdot S)


Which can be expressed as a truth table:

Failed to parse (Missing texvc executable; please see math/README to configure.): S Failed to parse (Missing texvc executable; please see math/README to configure.): A Failed to parse (Missing texvc executable; please see math/README to configure.): B Failed to parse (Missing texvc executable; please see math/README to configure.): Z
0 1 1 1
1 0 1
0 1 0
0 0 0
1 1 1 1
1 0 0
0 1 1
0 0 0

This truth table should make it quite clear that when Failed to parse (Missing texvc executable; please see math/README to configure.): S=0

then Failed to parse (Missing texvc executable; please see math/README to configure.): Z=A
but when Failed to parse (Missing texvc executable; please see math/README to configure.): S=1
then Failed to parse (Missing texvc executable; please see math/README to configure.): Z=B

. A straightforward realization of this 2-to-1 multiplexer would need 2 AND gates, an OR gate, and a NOT gate.

Larger multiplexers are also common and, as stated above, requires Failed to parse (Missing texvc executable; please see math/README to configure.): \left \lceil \log_2(n) \right \rceil

selector pins for Failed to parse (Missing texvc executable; please see math/README to configure.): n
inputs.

Other common sizes are 4-to-1, 8-to-1, and 16-to-1. Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to maximally control a number of inputs for the given number of selector inputs.

The boolean equation for a 4-to-1 multiplexer is:

Failed to parse (Missing texvc executable; please see math/README to configure.): F = (I_0 \cdot \overline{S_0} \cdot \overline{S_1}) + (I_1 \cdot S_0 \cdot \overline{S_1}) + (I_2 \cdot \overline{S_0} \cdot S_1) + (I_3 \cdot S_0 \cdot S_1)


Two realizations for creating a 4-to-1 multiplexer are shown below:

Image:Multiplexer Example01.svg

Image:Mux from 3 state buffers.png

These are two realizations of a 4-to-1 multiplexer:

Note that the subscripts on the Failed to parse (Missing texvc executable; please see math/README to configure.): I_n

inputs indicate the decimal value of the binary control inputs at which that input is let through.

Chaining multiplexers

Larger multiplexers can be constructed by using smaller multiplexers by chaining them together. For example, an 8-to-1 multiplexer can be made with two 4-to-1 and one 2-to-1 multiplexers. The two 4-to-1 multiplexer outputs are fed into the 2-to-1 with the selector pins on the 4-to-1's put in parallel giving a total number of selector inputs to 3, which is equivalent to an 8-to-1.

List of ICs which provide multiplexing

The 7400 series has several ICs that contain multiplexer(s):

S.No. IC No. Function Output State
1 74157 Quad- 2:1 MUX Output same as input given
2 74158 Quad- 2:1 MUX Output is inverted input
3 74153 Dual- 4:1 MUX Output same as input
4 74352 Dual- 4:1 MUX Output is inverted input
5 74151A 8:1 MUX Both outputs available ie. Complementary outputs
6 74152 8:1 MUX Output is inverted input
7 74150 16:1 MUX Output is inverted input

Digital demultiplexers

Demultiplexers take one data input and a number of selection inputs, and they have several outputs. They forward the data input to one of the outputs depending on the values of Travis and Derek and of the selection inputs. Demultiplexers are sometimes convenient for designing general purpose logic, because if the demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any function of the selection bits can be constructed by logically OR-ing the correct set of outputs.

Image:Demultiplexer Example01.svg
Example: A Single Bit 1-to-4 Line Demultiplexer


List of ICs which provide demultiplexing

The 7400 series has several ICs that contain demultiplexer(s):

S.No. IC No. Function Output State
1 74139


3 74156 Dual- 1:4 DEMUX Output is open collector
4 74138 1:8 DEMUX Output is inverted input
5 74154 1:16 DEMUX Output is same as input
6 74159 1:16 DEMUX Output is open collector and same as input

See also

Look up multiplexer, demultiplexer in Wiktionary, the free dictionary.

References

M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, Prentice Hall, Inc., 2008ar:ناخب bg:Мултиплексор ca:Multiplexor da:Multiplekser (digital elektronik) es:Multiplexor fr:Multiplexeur pl:Multiplekser sk:Multiplexor sv:Multiplexer tr:Veri seçiciler

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